Automatic Parallelization of Full 2-D Block Matching for Real Time Motion Compensation and Mapping into Special Purpose Architectures

The most important issue in video encoding is motion compensation within a frame sequence. Block matching techniques are used by various algorithms [5], [6] to estimate the motion into succesive frames. Full search 2D block matching is the most widely used algorithm for video encoding in all standards (H261, MPEG1-2 , HTDV etc). It provides with the best SNR, since it uses exhaustive search to find the best, in terms of MAD or MSE matching candidate block. Its main disadvantage is that it requires a lot of computations which should be performed for every candidate frame. Consequently, real time application of the 2-DFS algorithm for video compression, requires the use of parallel architectures, to achieve large amount of computations. This paper presents the application of automatic loop parallelization techniques to provide with scalable or fixed systolic arrays, with optimal performance, in terms of total computation time. We transform the BMA algorithm into an equivalent form, in order to apply the automatic parallelization method. Starting from the dependence index space, we map the matching algorithm to 2-D or 3-D systolic arrays and we propose an alternative mapping for fixed size architectures.